1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to a method for feed-forward control of an etch processing tool.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today""s manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of steps that must be accurately executed to produce useful semiconductor devices. To maintain proper manufacturing control, a number of inputs are generally used to fine-tune the steps.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are significantly different from one another and specialized to the point that the processes may be readily performed in different manufacturing locations that contain different control schemes.
Among the factors that affect semiconductor device manufacturing are wafer-to-wafer variations, start-up effects of manufacturing machine tools, and memory effects of manufacturing chambers. One of the process steps adversely affected by such factors is etch processing of semiconductor wafers.
Those skilled in the art will appreciate that etch processing may be used in conjunction with other semiconductor processing techniques, such as photolithography, deposition, and the like, to produce various circuit geometries on a surface of a wafer. Generally, etch processing comprises exposing at least a portion of the wafer to an etchant material. For example, features may be defined on a surface of the wafer through the use of a selectively patterned protective coating, such as photoresist, and by performing one or more etching processes. The protective coating is patterned to expose portions of the surface of the wafer to the etchant material. The exposed portions are removed during the etching process to produce the desired circuit geometries on the surface of the wafer.
Referring to FIG. 1, a cross-sectional view of a wafer 10 shown. In this illustrative embodiment, the wafer 10 comprised of a substrate 12, a stop layer 14, and an etch layer 16. Those skilled in the art will appreciate that, as a result of any number of processing variables, the etch layer 16 of the wafer 10 may become non-uniform, (e.g., its thickness may vary across the layer, its surface may be uneven or wavy, etc.) Although any number of surface topographies may manifest in the wafer 10 during processing, the wafer 10 generally exhibits center-to-edge non-uniformity after a chemical mechanical polishing operation is performed on the surface 17 of the etch layer 16. For example, as shown in FIG. 1, the thickness of the etch layer 16 may gradually increase from the center to the outer edge of the wafer 10, which is typically referred to as center-thin non-uniformity. Because of the center-thin non-uniformity of the etch layer 16, during an etching process, the portion of the etch layer 16 located at the center of the wafer 10 may be removed sooner than the portion of the etch layer 16 located at the outer edge of the wafer 10.
In FIG. 2, a trench 18 may be formed by selectively exposing the wafer 10 to a timed etching process. Those skilled in the art will appreciate that the duration of the etching process may vary depending upon, among other things, the thickness of the etch layer 16. Generally, the duration of the etching process is an engineering design decision based on approximations that may not adequately account for the non-uniformity of the etch layer 16 and other processing variables, such as wafer coverage of the etch layer 16, the non-uniformity of the etching process, and the like. In this embodiment, because of the center-thin non-uniformity of the etch layer 16, a portion of the stop layer 14 may be removed during the etching process. The degree to which the etching process is continued after the etch layer 16 is completely removed is called overetch. The amount of overetch is illustrated by the distance xe2x80x9cx.xe2x80x9d
Referring to FIG. 3, another cross-sectional view of a wafer 20 is shown. The wafer 20 may be comprised of a substrate 12, a stop layer 14, and an etch layer 16. Again, although a variety of surface topographies may manifest in the wafer 20 during manufacturing, the wafer generally exhibits center-to-edge non-uniformity. In this illustrative embodiment, the thickness of the etch layer 16 may gradually decrease from the center to the outer edge of the wafer 20, which is typically referred to as center-thick non-uniformity. Because of the center-thick non-uniformity of the etch layer 16, during an etching process, the portion of the etch layer 16 located at the edge of the wafer 20 may be removed sooner than the portion of the etch layer 16 located at the center of the wafer 20.
In FIG. 4, a trench 18 may be formed by selectively exposing the wafer 20 to a timed etching process. Again, the duration of the etching process may be an engineering design decision based on approximations. In this embodiment, because of the center-thick non-uniformity of the etch layer 16, a portion of the etch layer 16 may not be removed from the trench 18. The degree to which the etch layer 16 is not completely removed is called incomplete etch. The amount of incomplete etch is illustrated by the distance xe2x80x9cy.xe2x80x9d
Unfortunately, because of the possible non-uniformity and other processing variables, determining duration times for various etching processes is extremely difficult. For example, the duration of the etching process must adequately account for the non-uniformity of the wafer and other processing variables. One such processing variable includes etch rate non-uniformity of an etch processing tool. For example, during an etching process, the etch rate across the surface of a wafer may be non-uniform. In one embodiment, because of the surface non-uniformity of a wafer (e.g., center-thin, center-thick, etc.), the non-uniformity of the etching process may result in extreme overetch or incomplete etch of the wafer. For example, if the surface topography of a wafer is center-thin and the etch rate is center-fast, the center of the wafer may be severely overetched.
In one embodiment, with center-thin surface non-uniformity of a wafer, a degree of overetch at the center of the wafer may be required to ensure that the outer edge of the wafer is sufficiently etched. Alternatively, with center-thick surface non-uniformity of a wafer, a degree of overetch at the outer edge of the wafer may be required to ensure the center of the wafer is sufficiently etched.
Generally, when processing a wafer it is desirable to minimize overetch and incomplete etch. For example, it may be undesirable to overetch unnecessarily because the underlying layer is typically thinned during overetch, which may result in a decreased production yield. In addition, incomplete etch of wafers may also result in a decreased production yield.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided. The method includes measuring a surface non-uniformity of a wafer. A current state of an etch processing tool is determined. The surface non-uniformity of the wafer is compared with the current state of the processing tool. An operating parameter of the processing tool is adjusted based on the comparison of the surface non-uniformity of the wafer with the current state of the processing tool.
In another aspect of the present invention, a system is provided. The system includes a processing tool, a plurality of measuring devices, and a process controller. The processing tool is adapted for etch processing of a wafer. The plurality of measuring devices measure a surface non-uniformity of the wafer and determine a current state of the processing tool. The process controller compares the surface non-uniformity of the wafer with the current state of the processing tool and adjusts an operating parameter of the processing tool based on the comparison.